At the International Symposium on Circuits and Systems (ISCAS 2026) held in Shanghai, a premier academic event for global semiconductor scholars, He Tingbo, a Huawei director and President of its Semiconductor Business Unit, delivered a keynote speech titled "Exploring and Practicing New Semiconductor Paths." During this speech, she officially introduced the "Tau (τ) Law."
This marks the first time China has proposed new principles guiding industrial development in the global semiconductor field, presenting a comprehensive new theoretical framework for the continuous improvement of chip performance.
However, before discussing what the "Tau Law" entails, a fundamental question must be answered: why is a "new" law needed at all?
This brings us back to a dilemma known to all but understood by few: has Moore's Law truly reached its end?
What conceptual shift does the "Tau Law" represent? The issue isn't that Moore's Law itself is "dead," but that its underlying logic of "geometric scaling" is hitting physical limits.
For over half a century, the semiconductor industry's rule was simple: make transistors smaller, pack more components into the same area, and performance automatically improves, power consumption decreases, and costs are reduced. This logic held for nodes down to several tens of nanometers. However, progressing from tens of nanometers to single-digit nanometers has seen physical challenges and engineering costs increase exponentially.
Specifically, as process nodes approach 2nm and 1nm, individual atoms become significant hurdles. Quantum tunneling effects cause disruptive "leakage," where electrons pass through barriers they shouldn't. Controlling current becomes increasingly difficult, making power consumption and heat dissipation major challenges. Factory construction costs soar, with a single 3nm fab now costing at least $20 billion, reducing the number of global players capable of such investment from dozens to just a handful.
While the marginal returns of scaling are diminishing sharply, the demand for computing power from AI, large models, and autonomous driving is growing exponentially. This widening gap is the fundamental problem Huawei's "Tau Law" seeks to address.
He Tingbo's answer is: stop focusing solely on "size" and start focusing on "time."
This is the core shift of the "Tau Law": replacing "geometric scaling" with "temporal scaling."
The Four-Level Optimization of the "Tau Law" "Temporal scaling" may sound abstract, but its breakdown is straightforward. In the semiconductor world, a chip's performance and transistor density are ultimately determined by a factor called the "time constant τ" (the Greek letter tau, pronounced "Tao" in Chinese). It represents the time required for a signal to travel from one point to another within a chip. The faster the signal travels, the shorter its path, and the lower its latency, the more data can be processed per unit time, naturally leading to higher transistor density and performance.
Historically, the industry's approach to improving performance was to "make transistors smaller," allowing for denser wiring and shorter signal travel distances. Huawei's approach is different: achieve the same effect by systematically compressing signal propagation delay without significantly shrinking transistor size.
This concept is akin to optimizing traffic flow during rush hour. Instead of widening roads (increasing size), the focus is on optimizing traffic lights, implementing tidal flow lanes, and building overpasses or tunnels to streamline traffic, thereby naturally increasing vehicle speed.
The core technology enabling this approach for Huawei is "logic folding."
Traditional chip circuit layouts are two-dimensional, with signals traversing laterally across the plane, spending significant time on interconnects. The essence of logic folding is expanding the circuit layout from a "single floor" to "multiple floors." By "folding" critical paths that require long horizontal connections and stacking them vertically, the physical distance for signal propagation is dramatically shortened.
Logic folding is just one key lever within Huawei's multi-level collaborative system. Based on Huawei's previously disclosed technology roadmap, the "Tau Law" constructs a four-level optimization system spanning devices, circuits, chips, and systems.
At the foundational device level, Huawei optimizes transistor resistance and parasitic capacitance, minimizing the time constant τ from the physical layer to build a solid base.
At the circuit level, logic folding technology breaks through the physical boundaries of traditional planar layouts, transforming circuits from single-layer to dual-layer or even multi-layer structures.
At the chip level, Huawei introduces full-stack co-design encompassing "software, architecture, and chip." This approach allocates instruction and data flows based on actual workloads, ensuring the chip only computes what is necessary, reducing wasteful overhead, and minimizing end-to-end execution time.
At the top system level, Huawei has defined the "Lingqu Bus," re-architecting computing system interconnect protocols to achieve "super-node unified memory addressing and native memory semantics." This allows data exchange between different computing units to proceed with minimal "congestion."
These four levels are not optimized in a linear, sequential manner but are interlocked like gears. To use an analogy, the traditional chip optimization path is like desperately piling sports cars onto an increasingly narrow road. The "Tau Law," however, expands the roadmap to a broader dimension: devices, circuits, chips, and systems co-evolve, enabling signals to travel faster and computation to become smarter.
The High-End Chip Goals of the "Tau Law" The ultimate validation of the "Tau Law" lies in its products.
In her speech, He Tingbo provided a key figure: over the past six years, Huawei has successfully designed and mass-produced 381 different chips based on this path, covering various fields including communications, computing, terminals, and automotive. This track record forms a significant foundation for the credibility of Huawei's "Tau Law" theory.
What truly excites the market is the next-generation Kirin mobile chipset scheduled for release this autumn. According to He Tingbo, this chip will fully adopt logic folding technology, based on a new free logic design concept, expanding from a single layer to a dual layer, achieving a substantial leap in transistor density and system performance.
He Tingbo stated: "We have achieved a series of advancements that would be difficult to attain solely through advanced process technology." This suggests Huawei may have successfully navigated a path independent of those taken by Taiwan Semiconductor Manufacturing, Samsung, and Intel.
She also revealed a longer-term goal: by 2031, high-end chips based on the "Tau Law" will achieve transistor density equivalent to that of a 1.4nm process node. This means Huawei aims to achieve integration density and computing capability on par with 1.4nm process technology through system-level temporal optimization.
Is this a viable path? He Tingbo's words were: "Our solution is viable and sustainable. The performance of our new chips can continuously compete with the other path."
New Technology Waves in the Global Semiconductor Industry If the "Tau Law" can be understood as a paradigm shift from "space" to "time," then another major trend in the global semiconductor industry is the shift from "planar" to "three-dimensional."
Interestingly, these two trends are converging at the same point in time.
A wave of technologies represented by advanced packaging, Chiplet heterogeneous integration, and hybrid bonding is reshaping chip performance boundaries at an unprecedented pace and scale. Their core rationale aligns with that of the "Tau Law": rather than relying on the infinite scaling of transistors themselves, they drive continuous leaps in system-level performance through smarter integration and interconnection methods.
First, consider advanced packaging. If discussions about "how many nanometers" defined the industry for decades, the focus from 2024 to 2026 is rapidly shifting toward advanced packaging. According to Yole Group, the global advanced packaging market is projected to reach approximately $53.1 billion in 2025, with expectations to grow to $79.4 billion by 2030, representing a compound annual growth rate (CAGR) of about 8.4%. More striking is the growth rate of 2.5D/3D packaging, with a CAGR of 37% projected between 2023 and 2029.
Why such rapid growth? The reason is straightforward: explosive demand for AI chips. Advanced packaging, exemplified by Taiwan Semiconductor Manufacturing's CoWoS, places GPU cores and high-bandwidth memory (HBM) in close proximity, compressing signal transmission distances from the millimeter to the micrometer scale. This serves as the "invisible foundation" for the computing power explosion in the era of large AI models. Data indicates that global capacity for 2.5D and 3D advanced packaging remains insufficient to meet demand, with lead times for some orders exceeding one year and a supply gap estimated at around 23%. Leading global manufacturers are embarking on massive expansion efforts: Taiwan Semiconductor Manufacturing plans to establish seven advanced packaging fabs, aiming to increase annual capacity from 1.3 million wafers to 2 million wafers by 2027, a roughly 53.85% increase.
Next, consider Chiplets. The logic behind this technology is to break down a large monolithic chip into multiple smaller chiplets, each manufactured using the optimal process node, and then "bond" them together via advanced packaging—similar to "cutting a large chessboard into smaller puzzle pieces and reassembling them." Chiplet architecture is already widely deployed in AI chips. For domestic chip manufacturers, this technology holds particular strategic significance: it allows critical core modules to use advanced process nodes while employing mature nodes for non-critical I/O and memory modules. This effectively mitigates limitations in accessing advanced processes, achieving "system-level performance with finite resources."
If Chiplets are about "building blocks," then hybrid bonding is the "glue" that determines whether these blocks can be stacked stably and densely. The breakthrough of hybrid bonding lies in its elimination of solder bumps, enabling direct copper-to-copper contact at the atomic level for direct bonding between chips. Compared to traditional thermal compression bonding, hybrid bonding can increase interconnect density by one to two orders of magnitude, with extremely low parasitic capacitance, significantly reducing signal delay and power consumption.
This technology is viewed by the industry as "an essential technology roadmap for the next decade in the post-Moore era." In terms of practical implementation, memory giants are fully engaged. SK hynix and Samsung are paving the way for next-generation HBM, with hybrid bonding expected to be introduced starting with HBM4. Validation of 16-layer HBM stacked structures is underway. The hybrid bonding equipment market is projected to grow at a CAGR of 69%, far exceeding the overall semiconductor industry growth rate.
There is an even more cutting-edge direction: silicon photonics interconnection and co-packaged optics (CPO).
The fundamental bottleneck in signal transmission is shifting from within chips to interconnections between chips and even between server racks. Traditional copper interconnects suffer from high loss at high frequencies and limited distance, increasingly struggling to meet the bandwidth demands of large-scale AI clusters. The core idea of silicon photonics is to use light instead of electrical signals for transmission, offering higher speed, lower latency, and significantly reduced power consumption.
At a technology forum in May 2026, Taiwan Semiconductor Manufacturing prominently disclosed its "three-layer cake" AI platform architecture: the bottom layer is the compute layer, the middle is the packaging integration layer (CoWoS/SoIC), and the top layer is the "most important for the future" photonic interconnect layer (COUPE). COUPE technology employs 3D heterogeneous integration to vertically stack electronic and photonic chips, bringing components extremely close together and drastically reducing electrical coupling loss. According to Taiwan Semiconductor Manufacturing, mass production of the world's first 200Gbps micro-ring modulator using COUPE technology has commenced this year, with a bit error rate below one in 100 million. Compared to traditional copper wires, COUPE can improve system energy efficiency by 4 times and reduce latency by 10 times; when deeply integrated with the packaging platform, energy efficiency can improve by up to 10 times, with latency reduced by 20 times.
Guojin Securities explicitly stated in its latest research report: 2026 marks the first year of CPO industrialization. Core players in the supply chain like Taiwan Semiconductor Manufacturing, NVIDIA, and Broadcom are actively entering the field, signaling the formal commencement of large-scale deployment of "optics replacing copper" in AI data centers.
Conclusion In the long term, Huawei's "Tau Law" is highly aligned with the direction of the entire industry's technological evolution. Whether termed "temporal scaling" or "advanced packaging," the underlying essence reflects a fundamental consensus: improving chip performance can no longer rely solely on "making transistors smaller."
The real competition is shifting to a new set of dimensions: interconnect density, signal latency, system synergy, vertical stacking, and optical interconnection. The combinatorial effects of these dimensions are far more complex and expansive than simply shrinking a node. In Huawei's own words, from 2026 to 2035, as numerous exploratory technologies gradually become productized, transistor density will continue to increase, operating frequencies will continue to grow, and a steady stream of high-performance chips will emerge.
At the conclusion of her speech, He Tingbo made a meaningful statement: "The future certainly belongs to open cooperation. On the path of semiconductor evolution, no single enterprise can provide all the answers alone. Under the path of the 'Tau Law,' we look forward to close collaboration with global scientists, engineers, and industry partners to jointly promote the sustainable development of the semiconductor and electronics industries."
The semiconductor supply chain is too long and complex for any single country or company to dominate all segments. Every link—from semiconductor equipment including lithography machines, to packaging substrate materials, EDA tools, CPO standard systems—requires global collaboration. By proposing the "Tau Law," Huawei is offering the world a compatible, open, and alternative Chinese solution at a critical juncture when the semiconductor industry is searching for new growth curves.
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