Morgan Stanley's latest research report cuts through the noise surrounding AI infrastructure investment, providing answers to five core market concerns based on field research within the Asian supply chain. The analysis covers NVIDIA's Rubin Ultra packaging solution, foundry selection for LPUs, Samsung's shift of HBM base dies to TSMC, the implications of the Broadcom-Google partnership for MediaTek, and the real-world chip demand driven by new computing capacity deployments.
In the advanced packaging sector, Morgan Stanley indicates that Taiwan Semiconductor Manufacturing's dominance in CoWoS/SoIC continues to strengthen, with capacity expected to expand to 160,000-170,000 wafers per month by 2027, sufficient to handle the surge in computing demand. However, technical challenges such as interposer warping still need resolution for extra-large chips.
Regarding custom chips, MediaTek's development of a 3nm TPU (codenamed ZebraFish) for Google is progressing smoothly, with mass production anticipated in the second half of 2026. The report maintains its revenue forecasts of $1.6 billion for 2026 and $10 billion for 2027, suggesting this will be decisive for a valuation reassessment of MediaTek.
In the foundry landscape, NVIDIA is gradually introducing Samsung as a supplement to TSMC. A dual-supplier strategy is possible for the LP35 node in 2027, challenging the expectation of TSMC's exclusive hold on NVIDIA's advanced process nodes.
NVIDIA Rubin Ultra: 2 or 4 Dies per Package? The market is highly focused on whether NVIDIA's 2027 Rubin Ultra will utilize 2 or 4 compute dies within a single package. This fundamentally depends on whether TSMC's CoWoS-L technology can cost-effectively support chip designs up to 9 reticles in size—a configuration that would include 4 compute dies, 2 I/O dies, and 8 to 10 HBM stacks.
Whether Rubin Ultra ultimately uses a 2-die or 4-die configuration will not materially alter NVIDIA's consumption of TSMC wafer capacity. TSMC's CoWoS roadmap indicates support for 9-reticle designs by 2027 is technically feasible, but reliability issues like interposer warping must be solved. If this bottleneck persists, Intel's EMIB-T could potentially capture market share from TSMC in projects like Google's 2nm TPU.
NVIDIA LPU Demand Surge: Which Foundry Benefits? NVIDIA's Groq 3 LPU is scheduled for launch in the second half of 2026, featuring liquid-cooled LPX racks. Each cabinet will house 256 LPUs, with each chip containing 128GB of on-chip SRAM and 640 TBps of expanded bandwidth, targeting low-latency AI inference scenarios. The current LP30 version is manufactured on Samsung's 7nm process.
Supply chain investigations indicate that starting with the LP35 node (4nm)—scheduled for mass production alongside Rubin Ultra in 2027—NVIDIA may adopt a dual-supplier procurement strategy between TSMC and Samsung. The LP40 node (expected to be 3nm) is planned for launch with the Feynman platform in 2028 and will utilize discrete SRAM with TSMC's SoIC 3D stacking technology.
For SoIC capacity, TSMC expects to reach 14,000 wafers per month by 2026, increasing to 28,000 by 2027, and further expanding to 45,000 by 2028.
Will Korean HBM Base Dies Shift to TSMC's 3nm? Due to the need for extensive custom design and IP support for HBM4e and HBM5 base dies, TSMC's 3nm process is set to become a critical node for global HBM base die production by 2028.
Latest supply chain information suggests TSMC will convert an additional 10,000 to 20,000 units of 4/5nm capacity to 3nm at its Fab 18 Phase 3 facility, preparing for demand from Korean HBM suppliers for custom HBM4e and HBM5 base dies.
From an investment perspective, AI memory—including SRAM and HBM base dies—is expected to become a significant growth driver for TSMC starting in 2028.
Impact of Broadcom-Google Announcement on MediaTek's TPU Opportunity The partnership announcement between Broadcom and Google initially raised market concerns about MediaTek's strategic position in the TPU supply chain. However, the report clearly states that this development does not alter its positive outlook on MediaTek's 3nm TPU (ZebraFish).
Supply chain checks confirm that ZebraFish is on track for mass production in the second half of 2026. The assumption of 400,000 units shipped in 2026 (translating to approximately $1.6 billion in revenue) is considered "firmly achievable." The 3nm TPU is currently undergoing ECO modifications on several metal layers due to power consumption being slightly higher than expected, but this does not impact the mass production timeline. Google is concurrently conducting testing and validation. A new mask set incorporating the design changes will be used for mass production, expected to result in more stable chip performance and quality.
More importantly, the report has turned optimistic about MediaTek's ABF substrate supply for 2027, reiterating its highest market forecast: 2.5 million units shipped, contributing roughly $10 billion in revenue, and maintaining an "Overweight" rating.
Looking at the complete Google TPU shipment forecast, total volume is projected to grow from 2.4 million units in 2024 to 6 million in 2027 and 7 million in 2028. MediaTek's ZebraFish (v8, 3nm) and HumuFish (v10, 2nm) are expected to contribute significantly to the volumes in 2026 and 2027, respectively.
What Chip Demand is Implied by New Compute Deployments? Recent market announcements include numerous compute deployment plans, such as the 2GW project from the AWS-OpenAI collaboration and the 3.5GW project involving Google and Broadcom. Translating these large-scale power figures into specific wafer demand leads to a core conclusion: power availability is not the bottleneck for TSMC's chip demand; instead, the constraints are ABF substrate and HBM supply.
Calculations estimate that over the lifecycle of these projects, the implied total CoWoS consumption for TSMC would be approximately 953,000 wafers, with front-end 2nm and 3nm wafer consumption around 652,000 wafers. Assuming OpenAI-related contracts are executed over a three-year period, the annual CoWoS demand from these projects for TSMC is projected to reach 259,000 wafers by 2027.
Morgan Stanley believes this target is entirely achievable, as TSMC plans to expand its total CoWoS capacity to 160,000-170,000 wafers per month by the end of 2027, which is sufficient to cover this incremental demand.
Comments